Some embodiments of the invention are directed to an improved approach for implementing I/O rings and performing die size estimations.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
The EDA tools may also be used to perform early stage analysis and examinations of an electronic design. For example, the process of performing chip planning can be greatly facilitated if the designer or chip planning tool can predict the expected die size of the IC product. However, the die size of the IC product is significantly affected by the required configuration of the I/O ring needed to support the IC product. The I/O ring is a top-level component within which all I/O related logic is instantiated, and is usually positioned around the periphery of the IC chip. Typical components include, for example, I/O cells, power and ground cells, boundary scan registers (BSRs), pin structures, and/or other glue-logic structures. The IC core typically resides within the boundaries of the I/O ring, with the core typically including the internal blocks and connectivity of the IC chip.
Since the I/O ring creates the peripheral boundary of the IC chip, this means that the amount of space available for the core is greatly affected by the size of the I/O ring, and hence the size of the die is also greatly affected by the required dimensions of the I/O ring. The size of the die for the IC product must be large enough to hold the required I/O ring structures as well as the core structures. Clearly, the most efficient die size is the situation when the dimensions of the minimum I/O ring periphery creates enough interior space to exactly match the required space of the core. If the total size of the periphery for the I/O ring is greater than what is needed to implement the core, the design is said to be “I/O limited”. A design is “core limited” if the core requires more space than the minimum periphery required to implement the I/O ring.
Therefore, for planning purposes, it is very desirable for engineers and architects to be able to obtain an accurate estimate of the I/O ring configuration for the final IC product. One reason already presented is that accurate estimate of the I/O ring dimensions allows the engineer or architect to know the required die size for the product. Moreover, if the expected design is I/O limited, then the designer knows that there may be sufficient excess space in the design to include additional functionality within the core.
Conventionally, it has not been possible to obtain accurate estimate of the I/O ring configurations and die sizes at very early stages of a design process. One reason for this is because I/O rings are conventionally implemented much later in the design cycle, and hence have not been available in an accurate form at early stages of the design for chip planning or estimation purposes. Another reason is that I/O rings are typically constructed using a highly manually and complex process after much of the other portions of the design have already been implemented in detail.